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KS0165 multimedia audio 1 / 20 overview the KS0165 wavetable synthesizer with effect processor chip represents the state-of-the-art in multimedia audio technology. the KS0165 combines a high-quality 32-voice wavetable synthesizer, a powerful 16-bit cpu, mpu-401 compatibility, effect processor & 16k delay ram into a single chip. the audio performance of a typical KS0165 system compares favorably to the best multimedia audio solutions available today, but at a fraction of the cost. a typical KS0165 system provides 32 voices of 16-bit, 44.1 khz sample rate wavetable synthesis and effects such as chorus and reverb, mpu-401 compatibility, general midi, gs and mt-32 compatibility. with KS0165, a complete wavetable synthesizer may be implemented with as few as three ics. both serial and parallel midi interfaces are provided . features high-quality 32-voice wavetable synthesizer general midi compliant internal audio effects processor & 16k delay ram supports all common cdp d/a formats supports up to 8mbytes of sample memory supports 8-bit, 16-bit and compressed samples directly supports rom, sram and dram hardware-based roland mpu-401 emulation 16-bit embedded cpu minimizes host pc overhead integrated sram for embedded cpu integrated midi uart software-controlled sleep mode sequoia pegasus synthesizer firmware 100 pin qfp package fully software configurable comprehensive software developers kit ordering information device package temperature range KS0165 100-qfp 0 ~+70 c applications multimedia audio products musical synthesizers related products ks0175-1m 1mb sample rom ks0175-2m 2mb sample rom ks0175-4m 4mb sample rom kf353/d/s dual operational amplifier
KS0165 multimedia audio 2 / 20 block diagram 16-bit embedded cpu ha[11:0] haenl hiorl hiowl hrst hdbenl bas[1:0] mpu401 emulation hd[7:0] midi uart memory i/f ras* cas*[2:0] we*[1:0] md[15:0] ma[22:1] txd rxd addr[22:0] mpu-int uart-int sdat lrclk bclk configuration registers data[15:0] msiz[1:0],mtype hirq hrstpol datyp[1:0] host pc i/o interface synthesizer effect processor dryl[23:0] dryr[23:0] fx1[23:0] fx2[23:0] isa bus sram cas3* ma[12:0]
KS0165 multimedia audio 3 / 20 typical application KS0165 50 49 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 32 31 44 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma10 ma11 ma12 vss vdd ma13 ma14 ma15 ma16 ma17 ma18 ma19 ma20 ma2 ma1 md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 vdd vss md2 md1 md0 sdat lrckl bclk datyp1 datyp2 test1 test mtype msize1 msize0 ma21 ma22 we0 we1 ras cas0 cas1 cas2 selb vss vdd extclk hiowl hiorl haenl xi xo vss vdd hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 hdbenl ha1 ha0 samsung hrst hrstpol csl bas1 bas0 rxd txd hint vdd vdd vss vss ha9 ha8 ha7 ha6 ha5 ha4 ha3 ha2
KS0165 multimedia audio 4 / 20 pin assignment - 100-qfp pin assignment(continued) pin # pin name pin # pin name pin # pin name pin # pin name 1 ha1 26 ras 51 ma2 76 test1 2 ha0 27 we1 52 ma1 77 test 3 hdbenl 28 we0 53 md15 78 mtype 4 hd7 29 ma22 54 md14 79 msize1 5 hd6 30 ma21 55 md13 80 msize0 6 hd5 31 ma20 56 md12 81 hrst 7 hd4 32 ma19 57 md11 82 hrstpol 8 hd3 33 ma18 58 md10 83 csl 9 hd2 34 ma17 59 md9 84 bas1 10 hd1 35 ma16 60 md8 85 bas0 11 hd0 36 ma15 61 md7 86 rxd 12 vdd 37 ma14 62 md6 87 txd 13 vss 38 ma13 63 md5 88 hint 14 xo 39 vdd 64 md4 89 vdd 15 xi 40 vss 65 md3 90 vdd 16 haenl 41 ma12 66 vdd 91 vss 17 hiorl 42 ma11 67 vss 92 vss 18 hiowl 43 ma10 68 md2 93 ha9 19 extclk 44 ma9 69 md1 94 ha8 20 vdd 45 ma8 70 md0 95 ha7 21 vss 46 ma7 71 sdat 96 ha6 22 selb 47 ma6 72 lrckl 97 ha5 23 cas2 48 ma5 73 bckl 98 ha4 24 cas1 49 ma4 74 datyp1 99 ha3
KS0165 multimedia audio 5 / 20 25 cas0 50 ma3 75 datyp0 100 ha2
KS0165 multimedia audio 6 / 20 pin description pin name pin # type description host pc interface ha[9:0] 1 - 2, 93 - 100 i host address bits 9-0. these are the low 10 bits of the host pc address bus, which are decoded to control access the mpu-401. for ibm pc application, these pins should be connected directly to a[9-0]. alternatively, these pins may be tied to gnd, and a fully qualified chip select signal may be connected to the csl* pin instead. haenl 16 i host address enable. this is the host pc i/o enable. all i/o operations are ignored any time this signal is high. for pc applications, these pins should be connected directly to aen*. csl 83 i chip select. in most applications where the mpu-401 emulation is being used, the ks0164 address decoder will be used. however, if a non-standard address decode is required, or of a plug-n-play address decode is available, a fully qualified, active-low chip select signal may be connected to this pin instead. if this pin is not used, it must be pulled up to v dd . hd[7:0] 4 - 11 i/o buffered host pc data bus bits [0:7]. these pins have 18ma drivers, so they may be directly connected to the host pc data bus in most applications. if additional buffering is desired a 74ls245 may be used with its enable pin connected to hdben*, and its dir pin connected to hior*. hiorl 17 i host i/o read. this is the host pc i/o read enable. hiowl 18 i host i/o write. this is the host pc i/o write strobe. data is written to internal registers on the rising edge of this signal. hrst 81 i host pc reset. the active polarity of this pin is programmable via the hrstpol pin. for pc application, this pin should be connected directly to the pc-bus rstdrv signal. for daughter card applications, connect this pin to the reset signal from the host board. hrstpol 82 i determines the signal polarity of the hrst pin. set this pin low to make hrst active low (typical for daughter card applications), set this pin high to make hrst active high (use for isa bus applications). hdbenl 3 o host pc data bus buffer enable. this output controls the enable to the 74ls245 which buffers the host pc data bus. this pin is driven low any time the mpu-401 is addressed for an i/o access. hint 88 o host mpu-401 interrupt. this is an active high interrupt output to the host pc. it should be connected to one of the host irq lines, normally irq2.
KS0165 multimedia audio 7 / 20 pin name pin # type description memory interface ma[22:1] 29 - 38 41 - 52 o memory address bus bits [22:1]. this is the external memory address bus. when accessing static memory devices (rom/sram), these pins will contain a stable address throughout the entire memory cycle. when accessing dynamic memory, pins ma[11:0] will contain the multiplexed dram address. md[15:0] 53 - 70 i/o memory data bus bit [15:0]. this is the external memory data bus. we1 27 o memory upper byte write enable. when this signal is low during an external memory access, it indicates that data bits md[15:8] should be written to the addressed memory device. we0 28 o memory lower byte write enable. when this signal is low during an external memory access, it indicates that data bits md[7:0] should be written to the addressed memory device. ras 26 o dynamic memory row address strobe. this signal is the row address strobe for all external dram. when a dram device is addressed, this signal will be driven low shortly after the row address has been placed on ma0-11. it will also be driven low during rom/sram cycles to provide cas-before-ras refresh for any dram devices in the system. cas2-0 23 - 25 o dynamic memory column address strobes/static memory chip selects [2:0]. when a dram device is addressed, one of these signals will be driven low shortly after the column address has been placed on ma[11:0]. it will also be driven low during rom/sram cycles to provide cas-before- ras refresh for any dram devices in the system. when a rom or sram device is addressed, one of these signals will be driven low shortly after the address has been placed on ma[22:0]. mtype 78 i memory type select. when this pin is tied to gnd, the optional memory device(s) connected to cas1 and/or cas2 are configured as static(rom or sram) devices. when this pin is pulled up to v dd , the optional memory device(s) connected to cas1 and/or cas2 are configured as dynamic (dram) devices. msize[1:0] 79,80 i dynamic memory size select. when optional dynamic memory is connected to cas1 and/or cas2, these pins configure the size of the dram devices so that proper address multiplexing can be performed by the ks0164. the size is configured as follows: msize1 msize0 dram size 0 0 64k 0 1 256k 1 0 1m 1 1 4m
KS0165 multimedia audio 8 / 20 pin name pin # type description d/a & effects processor interface sdat 71 o d/a converter serial data . these are the serial data outputs from the effect processor. sdat would be connected to the data input of an external 16-bit stereo serial d/a converter. bclk 73 o d/a converter bit clock. this is the bit clock for the external serial d/a converter for the synthesizer. lrclk 72 o d/a converter l/r clock. this is the l/r clock for the external serial d/a converter for the synthesizer. datype[1:0] 74, 75 i d/a converter serial data format select. these signals selects the data format of the d/a devices as follows: datype1 datype0 d/a data format 0 0 20bit i2s 0 1 16bit right-justified 1 0 20bit left-justified 1 1 20bit right-justified clock input xi 15 i 16.9344 mhz oscillator buffer input. this input will normally be connected to one side of a 16.9344mhz crystal, with a 20pf capacitor to ground. if desired, an externally generated 16.9344mhz clock may be connected to this pin instead. note that due to internal analog circuitry, the chip may not behave reliably if this clock input is not close to the design frequency. xo 14 o 16.9344 mhz oscillator buffer out. this input will normally be connected to one side of a 16.9344mhz crystal, with a 20pf capacitor to ground. if the osci pin is being driven by an externally generated clock, this pin should be left unconnected. power and ground vdd 12, 20, 39,66, 89,90 +5v digital power supply. vss 13, 21, 40, 67, 91,92 gnd digital ground.
KS0165 multimedia audio 9 / 20 pin name pin # type description miscellaneous rxd 86 i midi receive data. this is the ttl-level serial input to the 31.25 kbaud midi uart. for normal midi communication, this pin must be driven by an external opto-isolator from the current-loop midi line. txd 87 o ttl midi transmit data. this is the ttl-level serial output from the 31.25 kbaud midi uart. for normal midi communication, this pin must drive an external voltage-to-current converter to drive the current-loop midi line. bas[1:0] 84, 85 i mpu-401 base address select [1:0]. these pins select whether the mpu- 401 emulation will be decoded at address 320h, 330h, 340h, or 350h. bas1 bas0 address 0 0 320h 0 1 330h 1 0 340h 1 1 350h extclk 19 i test pin - manufacturing test pin. for normal operation, this pin must be tied to gnd. applying power to the device with this pin floating or tied to a logic high level may cause permanent damage to the device. test 77 i test pin - manufacturing test pin. for normal operation, this pin must be tied to gnd. applying power to the device with this pin floating or tied to a logic high level may cause permanent damage to the device. test1 76 i test pin - manufacturing test pin. for normal operation, this pin must be tied to gnd. applying power to the device with this pin floating or tied to a logic high level may cause permanent damage to the device. selb 22 i test pin - manufacturing test pin. for normal operation, this pin must be tied to gnd. applying power to the device with this pin floating or tied to a logic high level may cause permanent damage to the device.
KS0165 multimedia audio 10 / 20 general description the KS0165 is a highly integrated wavetable synthesizer chip, designed to be part of high- performance, low-cost multimedia audio systems. the chip contains a complete 32-voice, 16-bit, 44.1khz wavetable synthesizer with effect processor, a high-performance 16-bit cpu, compatibility with established standard audio interfaces, and all necessary system glue logic. with its on-chip cpu, an KS0165-based synthesizer imposes absolutely minimal host cpu overhead. its hardware-based mpu-401 emulation completely eliminates the memory overhead, software compatibility, and stability problems of tsr-based emulations. the following sections give a brief description of the major functional blocks of the KS0165. h ost pc i nterface all necessary isa bus interface logic is completely contained on-chip. this includes address decoding for the mpu-401 emulation, control signal interpretation, and optional data bus buffer control. all pc interface control logic operates completely asynchronously to the synthesizer/cpu logic. standard interfacing techniques are used to provide a highly compatible and reliable interface. the mpu-401 emulation can be decoded for any one of four standard address ranges, as selected by the bas[1:0] pins. in addition, a serial midi interface may be used, leaving the mpu-401 emulation inactive. this mode is particularly useful for stand- alone synthesizer modules and waveblaster-type daughter board applications. to better support non-pc-based applications, including stand-alone applications where no host cpu is available, the reset signal polarity is programmable via the hrstpol pin, to accommodate existing active high or active low reset signals. mpu-401 i nterface the primary interface for communicating midi data to/from the KS0165 is the on-chip mpu-401 emulation. this emulation provides the full hardware functionality and partial software functionality of a real mpu-401. mpu-401 uart mode is fully supported, while a subset of the "intelligent" mode commands are also supported. the intelligent mode support currently provided is adequate to support virtually all existing mpu-401 applications. all hardware necessary to support full intelligent mode is present, allowing more complete intelligent mode software support to be added in the future if it become necessary. the mpu-401 interface is used for communicating midi and command data between the pc and the on-board synthesizer, the pc and external devices connected to the on-board midi interface available through the joy stick connector on the card bracket. normally, the midi uart under the control of the embedded cpu, so that it can provide fifo buffering of midi data. however, the uart transmitter can also be directly connected to the mpu-401 emulation. this allows uart mode data transfers from the pc to external midi devices to take place with no intervention on the part of the cpu, although the cpu will still intercept and process mpu-401 command data and uart receive data. it is also possible for the on- board synthesizer to directly process midi data from external sources, if desired. unlike a real mpu-401, the emulation provides the optional capability of generating transmit interrupts to the pc for enhanced performance. midi uart i nterface the second of available interfaces for communicating midi data to/from the KS0165 is the on-chip of midi uart. this interface is always active, and works independently from the mpu-401 emulation, allowing the KS0165 to easily be used in stand-alone midi modules and waveblaster-type daughter board applications. e mbedded cpu in sharp contrast to many other low-cost multimedia audio solutions currently available, the ks0164 does not rely on the host pc processor or a slow external micro controller to drive the wavetable synthesizer. rather, the ks0164 contains a high-performance custom-built 16-bit cpu incorporating such advanced features as six different addressing modes, a hardware multiplier, a barrel shifter, and a peak execution rate of nearly 3 million instructions per second. in addition to providing optimal synthesizer audio quality, this reduces host pc cpu overhead and the resulting degradation of application/game performance. the considerable
KS0165 multimedia audio 11 / 20 memory overhead, compatibility problems, and erratic audio quality associated with tsr-based solutions are also completely eliminated. in addition to handling the myriad chorus associated with operating the wave table synthesizer, the embedded cpu is also responsible for performing much of the work of mpu-401 emulation. unlike a purely hardware-based solution, this makes possible future software updates to support additional functionality, such as full mpu-401 intelligent mode support. s ynthesizer the synthesizer extends and improves upon the functionality of the ks0164. the basic function remains unchanged. but the following areas are changed. the ks0164 digital filter worked quite well, but at very low cutoff frequencies cutoff coefficient is sensitive. at very low cutoff frequency, a single-bit change in the coefficient created audible artifacts. this made low-frequency filter sweeps all but impossible. in filter calculation datapath was very easy to generate arithmetic overflow. this makes unpleasant audio effects. to correct this, the internal datapath have been expanded to 18 bits. because the KS0165 has a internal effect processor, it provide a proper interface with effect processor. the specification for the synthesizer are follows: architecture : digital wavetable synthesizer voices : 32 polyphony : 32 note maximum multi timbral capability : up to 16 parts sample memory : up to 16 mwords of rom/sram/dram available sample sets : 1m*16bits, 512*16bits d/a converter : 16bit linear serial converter, all common data formats supported sample playback rate : fixed @ 44.1khz level & panning controls : separate 16bit l&r volume control for each voice filters : 2 separate 2 pole resonant digital filter for each voice data formats : 8/16-bit signed linear or 8/12-bit compressed envelopes : hardware envelopes for amplitude and filters effects : reverb, chorus( down load effect algorithm) firmware : sequoia development group pegasus compatibility : roland mt-322 sound set compatible customized sound sets available e ffect p rocessor & d elay r am KS0165 provides effects sound to d/a by embedded effects synthesizer. effects algorithm is downloaded by host cpu from external mask rom. it generates reverb, chorus and other effects. KS0165 does not need any external sram & delay ram which are used by buffer and effect delay ram.
KS0165 multimedia audio 12 / 20 general description(continued ) the specifications for the synthesizer are as follows: architecture digital wavetable synthesizer voices 32 polyphony 32 notes maximum multi-timbral capability up to 16 parts sample memory up to 24 mbytes of rom/sram/dram available sample sets 2mx16-bits, 1mx16-bits, 512kx16-bits d/a converter 16-bit linear serial converter, all common data formats supported sample playback rate fixed @ 44.1 khz level and panning controls separate 16-bit l&r volume controls for each voice filters 2 separate 2-pole resonant digital filters for each voice data formats 8- or 16-bit signed linear or 8- or 12-bit compressed envelopes hardware envelopes for amplitude and filters effects effects loop provided for dsp multiple effects processor firmware sequoia development group pegasus synthesizer firmware compatibility fully general-midi compliant roland mt-32 sound set compatible s ystem t iming a nd c ontrol all timing is derived from a 16.9344 mhz crystal oscillator, or an externally generated oscillator of any frequency up to 33mhz. however, note that the internal midi uart baud rate is directly proportional to the system clock rate. at any crystal frequency other than 16.9344 mhz, the uart baud rate will not be correct . s ample m emory i nterface each memory access cycle consists of 3 cycles of the 16.9344 mhz master clock, or 177.15 nsec. this is adequate to allow use of 150 nsec rom, and 80 nsec dram. the memory interface supports a minimum of one and a maximum of three memory devices. the device connected to cas0 must be a rom. in general the cpu will execute entirely out of this rom, and most, if not all, synthesizer voices will also be playing primarily from this rom, although entirely ram-based systems can be supported with some additional logic. rom memory accesses are exploited to allow dram refresh to occur simultaneously with rom accesses by executing cas-before-ras refresh cycles on all dram banks in parallel with all rom/sram accesses. for systems with rom-based samples, this scheme provides adequate refresh for all dram in the system. for a totally dram-based system, it is necessary to allocate one synthesizer voice to perform dram refresh. for a combined rom/dram system, as long as at least two voices are playing samples from rom at all times, adequate refresh will be provided automatically, otherwise one voice must be dedicated to providing dram refresh.
KS0165 multimedia audio 13 / 20 register description direct-addressed registers mpu-401 d ata r egister r ead /w rite a ddress m nemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base+0 hmad d7 d6 d5 d4 d3 d2 d1 d0 d[7:0] mpu-401 data. mpu-401 c ommand r egister w rite o nly a ddress m nemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base+1 hmac c7 c6 c5 c4 c3 c2 c1 c0 c[7:0] mpu-401 command. mpu-401 s tatus r egister r ead o nly a ddress m nemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base+1 hmac rxrdy txrdy 1 1 1 1 1 1 rxrdy received data ready status 0 = received data is available in hmad 1 = received data is not available txrdy transmit data buffer ready status 0 = mpu-401 is ready to receive next data/command in hmad or hmac 1 = mpu-401 is not ready to receive next data/command
KS0165 multimedia audio 14 / 20 electrical specification absolute maximum ratings c haracteristics s ymbol m in m ax u nit supply voltage (measured to v ss ) v dd -0.5 +7.0 v input voltage (any pin) v in v ss -0.5 v dd +0.5 v ambient operating temperature range t opr 0 +70 c storage temperature range t stg -55 +150 c notes: 1. absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. functional operation under any of these conditions is not implied. dc electrical characteristics c haracteristics s ymbol m in t yp m ax u nit supply voltage (measured to gnd) v dd 4.75 5.0 +5.25 v digital input high voltage v ih 2.2 - v dd +0.3 v digital input low voltage v il v ss -0.3 - 0.8 v digital output high voltage (i oh =400 m a) v oh 2.4 - - v digital output low voltage (i ol =3.2ma) v ol - - 0.45 v input leakage high current i ih -10 0 10 m a input leakage low current* i il -10 0 10 m a supply current i cc - 100 250 ma pull-up resistance** r up 40 - 250 k w test condition : v dd =5.0v, v ss =0v, f osc =16.9344mhz, t a =25 o c. * for pins test, test1,mtype, msiz1-0, bas1-0, hrstpol, hrst, datype1-0 and csl. ** all input pins except ones in *.
KS0165 multimedia audio 15 / 20 electrical specification(continued) ac electrical characteristics c haracteristics s ymbol m in t yp m ax u nit memory cycle time t cyc - 177 - nsec memory address/control delay t dly - 15 - nsec memory read data setup time t rdsu 15 - - nsec memory read data hold time t rdh 0 - - nsec ras* active time t ras - 88 - nsec cas* active delay time t cdly - 29 - nsec cas* active time t cas - 59 - nsec row address setup time t rasu - 44 - nsec row address hold time t rah - 29 - nsec column address setup time t casu - 29 - nsec oscillator frequency f osc - - 16.9344 mhz
KS0165 multimedia audio 16 / 20 rom/sram memory interface timing dram memory interface timing mclk ma[11:0] din dout ras* cas* cs, we* t dly t cyc t rdsu t rdh t ras t cas t dly t rasu t rah t casu mclk ma[11:0] din dout ras* cas* cs, we* t dly t cyc t rdsu t rdh t ras t cdly t cas t dly
KS0165 multimedia audio 17 / 20 16 clocks 32-bit frame data formats left channel data 64-bit frame data formats b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b1 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 xx b15 b14 b13 b3 b2 b1 b0 xx xx xx xx xx xx xx b15 b14 b13 b3 b2 b1 b0 xx xx xx b15 b14 xx xx xx xx xx b0 xx xx xx xx xx xx b15 b14 b13 b3 b2 b1 b0 xx xx xx xx xx xx xx b15 b14 b13 b3 b2 b1 b0 xx xx b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 bclk (1.411mhz) 16 clocks left channel data bclk (2.822mhz) 32 clocks 32 clocks right channel data right channel data lrclk (44.1khz) lrclk (44.1khz) 32-bit i 2 s (datype[1:0] = 00) 32-bit nodelay (datype[1:0] = 01) 64-bit lj (datype[1:0] = 10) 64-bit rj (datype[1:0] = 11)
KS0165 multimedia audio 18 / 20 audio board design & pcb layout guidelines overview proper analog circuit design and pcb layout are essential to achieving optimum audio performance, as well as acceptable emi (fcc/vde) characteristics from pc audio boards. this document outlines the basic guidelines that should be followed to ensure acceptable performance in these critical areas. as a reference, please refer to the evaluation board schematics and pcb layout. design overview in order to achieve optimum audio performance, in terms of signal-to-noise ratio, noise, floor, and distortion, always provide separate analog and digital supplies and grounds. all digital components should be connected to vcc and gnd, directly from the pc bus connectors. single-ended analog circuitry, such as d/a converters, codecs, etc., should be operated from a separate +5v supply which is locally regulated down from the +12v supply available on the pc bus. all operational amplifiers should be powered by filtered 12v supplies derived from the 12v supplies available on the pc bus. operational amplifiers should never be operated from a single-ended supply. this will not only reduce the dynamic range and headroom, but also significantly degrade the signal-to-noise ratio. handling grounds for optimum audio performance, it would be most desirable to keep the analog and digital supplies and returns totally isolated from one another. however, for the sake of emi (fcc) performance, it is generally necessary to keep all supplies closely coupled. also, in a pc, there are a limited number of supplies to work from, and only a single gnd. these conflicting requirements are best met by allowing the digital and analog returns (gnd & agnd) to be directly connected at only a single location, preferably directly adjacent to the card bracket. this single connection should be a substantial one, at least 100-200 mils. this connection is indicated in the evaluation board schematics as a gndstrap component. ac coupling the returns by means of 1-10nf capacitors straddling the perimeter of the agnd /gnd planes, at intervals of no more than 1-1.5 ?, should provide the coupling necessary to prevent emi problems which can be caused by the separate ground planes. the db-15 connector shell must be securely connected to the gnd plane, and the connector must be securely screwed to the bottom of the bracket, while the top of the bracket should have a tab which is securely screwed of riveted to the agnd plane, thus referencing all outgoing signal lines to the (relatively) clean chassis ground at the bracket. in past designs, these techniques have consistently resulted in a > 10db margin relative to the fcc class-b limits. in the analog section, it is desirable to have two agnd planes, rather than a single agnd plane, and a single power plane. all analog supplies can be easily routed as normal traces, since the currents are very low. if possible, place the agnd planes on the outer layer, and do all signal and power routing on the two inner layers, to minimize noise pickup from adjacent boards. in smt designs, make layers 2 & 4 agnd planes, and place as much routing as possible on layer 3, minimizing exposed routing on layer 1. the agnd plane should completely underlie all analog circuitry, including and d/a or a/d converters or codecs. there should be no vcc or gnd routing, or unnecessary digital signal routing through the area covered by the agnd plane. analog signal routing proper component is essential to getting optimum audio performance. all traces should be kept as short and straight as possible. avoid running traces parallel to other traces for other than very short distances. keep any digital or clock traces as far as possible from a/d and d/a converters. to minimize noise pickup, all routing to op-amp inputs should be kept as short as possible. op-amp output signals are far less critical, being driven by a relatively low impedance source. avoid routing op- amp input and output signals near each other to prevent feedback problems. also, be sure to follow the supply bypassing guidelines below. never route an analog signal through a digital area, or vice- versa.
KS0165 multimedia audio 19 / 20 audio board design & pcb layout guidelines(continued) digital signal routing use of vias should be minimized, particularly on high speed signals, such as clocks. for this reason, hand-routing is strongly recommended, rather than using an auto-router. even the auto-routers available today will use far more vias than an experienced hand-router. our evaluation boards are all completely hand-routed. keep all unbuffered pc- bus signals as short as possible, preferably no more than 1-2 ?. also rigorously avoid passing digital signals over any splits in the planes. keep all crystals as close as possible to the other components to which they are connected, and, if possible, surround their traces with gnd traces. never allow an oscillator or clock signal to cross the gnd/agnd plane split! securely attach, by soldering, the crystal case to its associated ground plane, usually gnd. supply bypassing in the digital section of the board, be sure no vcc pin is more than about 1 ? from a bypass capacitor. in the analog section, this may be relaxed somewhat, but try to ensure that each supply pin is within at least 1.5-2 ? of a bypass capacitor. in both the digital and analog sections, evenly distribute the bypass capacitors, and use an even mix of 0.1 m f and 0.001 m f capacitors. for the KS0165, one bypass capacitor for each vcc pin is recommended. all bypass capacitors should be routed such that the connection is from the vcc and gnd planes to the capacitor, and then from the capacitor to the ic pins. emi suppression adequate emi suppression can most easily be achieved through careful pcb layout, and the use of small capacitors to gnd/agnd, rather than ferrite beads. since the analog input and output signal points are all (relatively) low impedance, small capacitors(1-10nf) can be connected between these points and agnd with no appreciable effect on audio performance. all such capacitors should be places as close as possible to the connectors, and the traces leaving them (going to the connectors) should not pass near any unfiltered traces which might couple-in unwanted high-frequency noise.
KS0165 multimedia audio 20 / 20 package dimensions (100-qfp-1420c) #1 0.65 0.30 0.10 (0.58) (0.83) 20.00 0.20 23.90 0.30 #100 14.00 0.20 17.90 0.30 0.80 0.20 2.65 0.10 3.00max 0.00min 0.80 0.20 0 - 8 0.15 +0.10 -0.05 0.10max 0.10max

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